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docs: add obsidian hwr docs

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theoleuthardt 2026-04-09 11:24:56 +02:00
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155
Digitaltechnik/Klausuruebung.circ Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.7.1" version="1.0">
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
<lib desc="#Wiring" name="0"/>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4">
<tool name="ROM">
<a name="contents">addr/data: 8 8
0
</a>
</tool>
</lib>
<lib desc="#I/O" name="5"/>
<lib desc="#Base" name="6">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="6" map="Button2" name="Menu Tool"/>
<tool lib="6" map="Button3" name="Menu Tool"/>
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="6" name="Poke Tool"/>
<tool lib="6" name="Edit Tool"/>
<tool lib="6" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin">
<a name="tristate" val="false"/>
</tool>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="main">
<a name="circuit" val="main"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif plain 12"/>
<wire from="(840,340)" to="(890,340)"/>
<wire from="(190,300)" to="(510,300)"/>
<wire from="(330,460)" to="(330,910)"/>
<wire from="(120,240)" to="(120,760)"/>
<wire from="(120,760)" to="(620,760)"/>
<wire from="(290,110)" to="(290,130)"/>
<wire from="(670,780)" to="(900,780)"/>
<wire from="(330,90)" to="(330,110)"/>
<wire from="(120,760)" to="(120,910)"/>
<wire from="(150,110)" to="(150,130)"/>
<wire from="(190,90)" to="(190,110)"/>
<wire from="(510,250)" to="(510,280)"/>
<wire from="(190,270)" to="(190,300)"/>
<wire from="(190,110)" to="(220,110)"/>
<wire from="(190,300)" to="(190,910)"/>
<wire from="(190,110)" to="(190,270)"/>
<wire from="(460,480)" to="(490,480)"/>
<wire from="(260,500)" to="(260,790)"/>
<wire from="(330,110)" to="(360,110)"/>
<wire from="(330,110)" to="(330,410)"/>
<wire from="(490,420)" to="(510,420)"/>
<wire from="(330,410)" to="(480,410)"/>
<wire from="(570,410)" to="(770,410)"/>
<wire from="(770,350)" to="(770,410)"/>
<wire from="(330,410)" to="(330,460)"/>
<wire from="(150,160)" to="(150,920)"/>
<wire from="(290,160)" to="(290,920)"/>
<wire from="(260,790)" to="(260,910)"/>
<wire from="(330,460)" to="(400,460)"/>
<wire from="(120,110)" to="(120,240)"/>
<wire from="(260,110)" to="(260,500)"/>
<wire from="(460,250)" to="(510,250)"/>
<wire from="(360,110)" to="(360,130)"/>
<wire from="(480,390)" to="(480,410)"/>
<wire from="(120,90)" to="(120,110)"/>
<wire from="(770,300)" to="(770,330)"/>
<wire from="(220,110)" to="(220,130)"/>
<wire from="(260,90)" to="(260,110)"/>
<wire from="(260,790)" to="(620,790)"/>
<wire from="(120,110)" to="(150,110)"/>
<wire from="(480,390)" to="(510,390)"/>
<wire from="(260,110)" to="(290,110)"/>
<wire from="(770,330)" to="(790,330)"/>
<wire from="(770,350)" to="(790,350)"/>
<wire from="(120,240)" to="(400,240)"/>
<wire from="(190,270)" to="(400,270)"/>
<wire from="(570,300)" to="(770,300)"/>
<wire from="(260,500)" to="(400,500)"/>
<wire from="(890,340)" to="(900,340)"/>
<wire from="(220,160)" to="(220,920)"/>
<wire from="(490,420)" to="(490,480)"/>
<wire from="(360,160)" to="(360,920)"/>
<comp lib="1" loc="(220,160)" name="NOT Gate">
<a name="facing" val="south"/>
</comp>
<comp lib="0" loc="(120,90)" name="Pin">
<a name="facing" val="south"/>
<a name="tristate" val="false"/>
<a name="label" val="A"/>
</comp>
<comp lib="1" loc="(150,160)" name="NOT Gate">
<a name="facing" val="south"/>
</comp>
<comp lib="1" loc="(670,780)" name="AND Gate"/>
<comp lib="1" loc="(360,160)" name="NOT Gate">
<a name="facing" val="south"/>
</comp>
<comp lib="0" loc="(260,90)" name="Pin">
<a name="facing" val="south"/>
<a name="tristate" val="false"/>
<a name="label" val="C"/>
</comp>
<comp lib="1" loc="(460,480)" name="XOR Gate"/>
<comp lib="1" loc="(570,410)" name="XOR Gate"/>
<comp lib="0" loc="(330,90)" name="Pin">
<a name="facing" val="south"/>
<a name="tristate" val="false"/>
</comp>
<comp lib="1" loc="(290,160)" name="NOT Gate">
<a name="facing" val="south"/>
</comp>
<comp lib="1" loc="(840,340)" name="AND Gate"/>
<comp lib="5" loc="(890,340)" name="LED"/>
<comp lib="0" loc="(190,90)" name="Pin">
<a name="facing" val="south"/>
<a name="tristate" val="false"/>
<a name="label" val="B"/>
</comp>
<comp lib="5" loc="(900,780)" name="LED"/>
<comp lib="1" loc="(460,250)" name="XOR Gate"/>
<comp lib="1" loc="(570,300)" name="XOR Gate"/>
</circuit>
</project>