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docs: add obsidian hwr docs
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theoleuthardt
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148
Digitaltechnik/DNF.circ
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148
Digitaltechnik/DNF.circ
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="2.7.1" version="1.0">
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This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<lib desc="#Wiring" name="0"/>
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<lib desc="#Gates" name="1"/>
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<lib desc="#Plexers" name="2"/>
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<lib desc="#Arithmetic" name="3"/>
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<lib desc="#Memory" name="4"/>
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<lib desc="#I/O" name="5"/>
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<lib desc="#Base" name="6">
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<tool name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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</lib>
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<main name="main"/>
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<options>
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<a name="gateUndefined" val="ignore"/>
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<a name="simlimit" val="1000"/>
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<a name="simrand" val="0"/>
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</options>
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<mappings>
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<tool lib="6" map="Button2" name="Menu Tool"/>
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<tool lib="6" map="Button3" name="Menu Tool"/>
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<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
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</mappings>
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<toolbar>
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<tool lib="6" name="Poke Tool"/>
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<tool lib="6" name="Edit Tool"/>
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<tool lib="6" name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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<sep/>
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<tool lib="0" name="Pin">
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<a name="tristate" val="false"/>
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</tool>
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<tool lib="0" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="labelloc" val="east"/>
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</tool>
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<tool lib="1" name="NOT Gate"/>
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<tool lib="1" name="AND Gate"/>
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<tool lib="1" name="OR Gate"/>
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</toolbar>
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<circuit name="main">
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<a name="circuit" val="main"/>
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<a name="clabel" val=""/>
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<a name="clabelup" val="east"/>
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<a name="clabelfont" val="SansSerif plain 12"/>
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<wire from="(770,310)" to="(770,320)"/>
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<wire from="(470,390)" to="(660,390)"/>
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<wire from="(190,390)" to="(190,910)"/>
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<wire from="(470,230)" to="(780,230)"/>
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<wire from="(290,110)" to="(290,130)"/>
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<wire from="(220,230)" to="(220,310)"/>
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<wire from="(850,340)" to="(890,340)"/>
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<wire from="(700,360)" to="(800,360)"/>
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<wire from="(150,110)" to="(150,130)"/>
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<wire from="(190,90)" to="(190,110)"/>
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<wire from="(120,290)" to="(420,290)"/>
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<wire from="(190,110)" to="(190,390)"/>
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<wire from="(780,230)" to="(780,310)"/>
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<wire from="(290,160)" to="(290,250)"/>
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<wire from="(190,110)" to="(220,110)"/>
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<wire from="(220,310)" to="(220,920)"/>
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<wire from="(150,210)" to="(150,370)"/>
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<wire from="(120,290)" to="(120,900)"/>
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<wire from="(150,370)" to="(150,920)"/>
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<wire from="(780,310)" to="(800,310)"/>
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<wire from="(130,920)" to="(150,920)"/>
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<wire from="(150,210)" to="(420,210)"/>
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<wire from="(150,370)" to="(420,370)"/>
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<wire from="(680,350)" to="(680,470)"/>
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<wire from="(280,920)" to="(290,920)"/>
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<wire from="(700,360)" to="(700,550)"/>
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<wire from="(290,250)" to="(420,250)"/>
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<wire from="(290,330)" to="(420,330)"/>
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<wire from="(290,410)" to="(420,410)"/>
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<wire from="(470,620)" to="(730,620)"/>
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<wire from="(660,330)" to="(800,330)"/>
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<wire from="(680,350)" to="(800,350)"/>
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<wire from="(220,160)" to="(220,230)"/>
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<wire from="(470,310)" to="(770,310)"/>
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<wire from="(290,250)" to="(290,330)"/>
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<wire from="(290,330)" to="(290,410)"/>
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<wire from="(120,90)" to="(120,110)"/>
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<wire from="(220,110)" to="(220,130)"/>
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<wire from="(260,90)" to="(260,110)"/>
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<wire from="(190,390)" to="(420,390)"/>
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<wire from="(470,550)" to="(700,550)"/>
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<wire from="(120,110)" to="(150,110)"/>
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<wire from="(260,110)" to="(260,910)"/>
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<wire from="(260,110)" to="(290,110)"/>
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<wire from="(770,320)" to="(800,320)"/>
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<wire from="(470,470)" to="(680,470)"/>
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<wire from="(150,160)" to="(150,210)"/>
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<wire from="(730,370)" to="(730,620)"/>
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<wire from="(730,370)" to="(800,370)"/>
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<wire from="(260,910)" to="(270,910)"/>
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<wire from="(120,110)" to="(120,290)"/>
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<wire from="(660,330)" to="(660,390)"/>
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<wire from="(290,410)" to="(290,920)"/>
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<wire from="(890,340)" to="(900,340)"/>
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<wire from="(220,230)" to="(420,230)"/>
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<wire from="(220,310)" to="(420,310)"/>
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<comp lib="1" loc="(470,230)" name="AND Gate"/>
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<comp lib="1" loc="(850,340)" name="OR Gate">
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<a name="inputs" val="6"/>
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</comp>
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<comp lib="1" loc="(220,160)" name="NOT Gate">
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<a name="facing" val="south"/>
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</comp>
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<comp lib="0" loc="(120,90)" name="Pin">
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<a name="facing" val="south"/>
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<a name="tristate" val="false"/>
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<a name="label" val="A"/>
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</comp>
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<comp lib="1" loc="(470,390)" name="AND Gate"/>
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<comp lib="1" loc="(150,160)" name="NOT Gate">
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<a name="facing" val="south"/>
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</comp>
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<comp lib="1" loc="(470,620)" name="AND Gate"/>
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<comp lib="1" loc="(470,550)" name="AND Gate"/>
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<comp lib="0" loc="(260,90)" name="Pin">
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<a name="facing" val="south"/>
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<a name="tristate" val="false"/>
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<a name="label" val="C"/>
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</comp>
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<comp lib="1" loc="(290,160)" name="NOT Gate">
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<a name="facing" val="south"/>
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</comp>
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<comp lib="1" loc="(470,470)" name="AND Gate"/>
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<comp lib="5" loc="(890,340)" name="LED"/>
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<comp lib="0" loc="(190,90)" name="Pin">
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<a name="facing" val="south"/>
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<a name="tristate" val="false"/>
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<a name="label" val="B"/>
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</comp>
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<comp lib="1" loc="(470,310)" name="AND Gate"/>
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</circuit>
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</project>
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